A simple collection of tips, tricks and traps that are either undocumented or appear to be somewhat obscured in the official documentation. Meant to be a one stop list that can be used to double check any assumptions during HW and SW design and debugging.

ToDo

• Provide reference links to documentation (where available) backing up the assertions here
• Add more items to the list

SPI

• The slave select pin (*SS) MUST be held high, and SSEL fuction selected, when using the SPI peripheral as master. Otherwise it will revert to slave only functionality.
• This problem has reportedly been fixed on LPC2131/2132/2138. On these devices, you can configure this bit for non-SPI function (e.g.: GPIO) when using SPI in master mode. See: [1].

A/D

• An input voltage > Vcc (nominally 3.3V) on any pin that can serve as an A/D input will confuse the A/D (even if a different function is selected for that pin). This problem is present in the following devices: LPC211x, 212x, 221x, 229x but NOT present in LPC213x and LPC214x

Security

• All LPC2000 devices introduced after the LPC2104, 2105, 2106 have a method to protect the flash contents.
• The 2104, 2105 and 2106 do not provide any method for protecting the flash against reading by an external programmer.

Pull-up

• The LPC21x4 and LPC21x9 have internal pull-ups on all P1.x pins. The Rev.02 datasheet doesn't mention pull-ups for P1.27-31.

Pin Toggle Timing

• Many people are surprised by the pin toggle speed on the LPC2000 series. Early measurments can be found on this thread [[2]]. An explanation has been given [[3]]. The latest additions to the family, the LPC214x family and the LPC2101/2/3 have much faster ports. With CPU-clock / 4 these are the fastest ARM7 micros out there for port toggling now

IAP (In Application FLASH Programming)

• Calls to IAP function must force Thumb mode (i.e.: use address 0x7ffffff1 - with low order bit set.) See User's Manual chapter "Flash Memory System and Programming" paragraph "IAP COMMANDS"
• Be sure the chip has the latest on-chip boot-loader software, as described in the chip's Erratasheet. (IAP functions are contained in the on-chip boot-loader software).

I2C

• Pins which can be used for I2C (SCL and SDA) have open drain outputs, even if a different function is selected for that pin. You may need to add pull-up resistors.

Timers / PWM

• There is a race condition problem when using more than one channel on a Timer or PWM Block. See: [4].
• If a pin is selected as a Timer Capture input, you cannot read the state of the pin. You have to change the Pin Function Select Register setting to GPIO in order to read the state (or tie the signal to an additional GPIO pin).
• PWM: The manual talks about the MRx shadow registers and how new MRx values don't take effect until the next MR0 event. If, however, you don't enable PWM mode (PWMTCR bit 3), writes to the MRx registers take effect immediately. You can then use the PWM to generate arbitrary jitter-free waveforms by updating the MRx registers in the MRx match interrupt handlers.

UART

• FIFO enable bit must be set for proper UART operation. (See Description of this bit in User Manual.)

External Interrupts

• If a pin is selected as an External Interrupt, you cannot read the state of the pin. You have to change the Pin Function Select Register setting to GPIO in order to read the state (or tie the signal to an additional GPIO pin).

Watchdog

• Although the WDEN and WDRESET bits in the Watchdog Mode Register cannot be cleared by software (to prevent run-away code from disabling the watchdog), the Watchdog Timer Constant Register is not similarly protected. If 0xFFFFFFFF were to get written to this register, the watchdog time would be almost 5 minutes (for 60 MHz pclk - longer for lower pclk frequency), effectively disabling the watchdog function.

5 Volt Tolerant I/O

• The i/o pins are 5V tolerant only when the 3.3V Vdd supply is present.
• An input voltage > Vdd (nominally 3.3V) on any pin that can serve as an A/D input will confuse the A/D (even if a different function is selected for that pin).

CAN

• The CAN controller has an Errata that does not allow to use Full-CAN. The LPC2_FullCAN.zip example in the file section of the LPC2000 Yahoo group provides a good idea for a work around. [5]

Crystal Oscillator/PLL setup

• For LPC210x, two recommended crystal frequencies are 14.7456 MHz and 15.000 MHz. 15 will give max PCLK (60 MHz) which is needed for high-resolution timing, however, if a UART is to be used, the 14.7456 MHz crystal will give better timing values for high baud rates (e.g. 0.0007% vs. 0.06% for 115200bps). Recommended PLL settings for the above crystal frequencies: PLL multiplier (MSEL) = 4, PLL divider (PSEL) = 2, and peripheral bus divider (APBDIV) = 1

Errata Sheet

• As always, it is highly recommended to check the Errata Sheet of the devices you want to use! [6]